发明名称 Method of reducing pattern pitch in integrated circuits
摘要 A method of reducing pattern pitch is provided. A material layer, a hard mask layer and a patterned photoresist layer are sequentially formed over a substrate. Using the patterned photoresist layer as etching mask, the hard mask layer is etched. Due to the trenching effect, a residual hard mask layer remains in an exposed region exposed by the photoresist layer and micro-trenches are formed at the edges of the residual hard mask layer. Thereafter, using the residual hard mask layer as etching mask to pattern the material layer. Finally, the patterned photoresist layer and the hard mask layer are removed. In the invention, the trenching effect is utilized when etching the hard mask layer. A portion of the hard mask layer remains, and the micro-trenches are formed in the hard mask layer. After the micro-trenches are transferred to the material layer, the pattern pitch can be reduced.
申请公布号 US7105099(B2) 申请公布日期 2006.09.12
申请号 US20040710488 申请日期 2004.07.14
申请人 MACRONIX INTERNATIONAL CO., LTD. 发明人 CHUNG HENRY;LIANG MING-CHUNG;WEI AN-CHI;TSAI SHIN-YI;WEI KUO-LIANG
分类号 B44C1/22;H01L21/00 主分类号 B44C1/22
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