发明名称 Adjustment of termination resistance in an on-die termination circuit
摘要 The on-die termination circuit of the present invention includes a main resistance circuit and an adjustment circuit. The main resistance circuit is provided with a resistance element and a transistor that is turned OFF when the on-die termination circuit is to be placed in the OFF state and turned ON when the on-die termination circuit is to be placed in the ON state. The adjustment circuit is provided with transistors that are both connected together in parallel and connected in parallel to the main resistance circuit, and that are turned ON or OFF when the on-die termination circuit is placed in the ON state so as to adjust the termination resistance of the entire on-die termination circuit.
申请公布号 US2006197551(A1) 申请公布日期 2006.09.07
申请号 US20060365885 申请日期 2006.03.02
申请人 ELPIDA MEMORY, INC. 发明人 KOBAYASHI SHOTARO
分类号 H03K19/003 主分类号 H03K19/003
代理机构 代理人
主权项
地址