| 摘要 |
PROBLEM TO BE SOLVED: To facilitate a DC test of an output buffer by suppressing increase in cell area or increase in delay time to the utmost. SOLUTION: The semiconductor integrated circuit is provided with the output buffers 21, 22, and 23A to be subjected to the DC test; FF circuits 11-13 connected to inputs of the output buffers, directly or via combination logic circuits 41 and 42; and selectors 51-53 connecting the plurality of FF circuits so that a shift register is constituted. During the DC test, the shift register is constituted by the FF circuits by means of the selectors 51-53 so that test pattern data can be inputted to the shift register. COPYRIGHT: (C)2006,JPO&NCIPI
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