| 摘要 |
A method for fabricating a trench power MOSFET, comprising an epitaxial layer and a mask layer formed over a substrate, a trench formed in the epitaxial layer and the mask layer, a gate oxide layer formed on the trench, then the mask layer removed, a body well region formed in the epitaxial layer beside the trench, a source region formed in and adjacent to the body well region, and a spacer formed on the sidewalls of the exposed gate layer exposing the source region partially. Masking by spacer, an opening exposing the body well is formed by partially removing the source region and the gate layer. A body region is formed in the body well region under the opening. A silicide layer is formed on the surfaces of the gate layer and the opening.
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