发明名称 Verification of embedded test structures in circuit designs
摘要 A program product for use in generating test benches for verifying test structures embedded in a circuit, comprises a verification specification processor for parsing a verification specification containing test specifications for selected test structures and a test bench generator for each of one or more types of embedded test structures, each test bench generator being operable to process a test structure specification of a test structure of a corresponding test structure type and generate a test bench using data contained in said test specifications of said verification specification, data contained in said test structure specification and data contained in a test connection specification.
申请公布号 US7103860(B2) 申请公布日期 2006.09.05
申请号 US20030349452 申请日期 2003.01.23
申请人 LOGICVISION, INC. 发明人 PRICE PAUL;COTE JEAN-FRANCOIS;VERMA AJIT KUMAR
分类号 G06F17/50;G01R31/3183 主分类号 G06F17/50
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