发明名称 Sizing and placement of charge recycling (CR) transistors in multithreshold complementary metal-oxide-semiconductor (MTCMOS) circuits
摘要 In one embodiment, a circuit includes a first row of circuit blocks that are each connected to a supply directly and to ground via a first sleep transistor. A connection between the first circuit block and the first sleep transistor is a virtual ground node. The circuit includes a second row of circuit blocks that are each connected to ground directly and to the supply via a second sleep transistor. A connection between the second circuit block and the second sleep transistor is a virtual supply node. The circuit includes a transmission gate (TG) or pass transistor connecting the virtual ground nodes to the virtual supply nodes to enable charge recycling between circuit blocks in the first row and circuit blocks in the second row during transitions by the circuit from active mode to sleep mode, from sleep mode to active mode, or both.
申请公布号 US7834684(B2) 申请公布日期 2010.11.16
申请号 US20080263312 申请日期 2008.10.31
申请人 FUJITSU LIMITED 发明人 FALLAH FARZAN;PAKBAZNIA EHSAN;PEDRAM MASSOUD
分类号 G05F1/10 主分类号 G05F1/10
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