| 摘要 |
A system and method for half-rate phase detecting are provided. The method comprises: receiving binary data; dividing the data by two; latching the divided data with a first half-rate clock, creating Q 1 ; latching the divided data with a second half-rate clock, the inverse of the first clock, creating Q 2 ; latching Q 1 with the second clock, creating Q 3 ; latching Q 2 with the first clock, creating Q 4 ; XORing Q 1 and Q 2 to create phase signals; and, XORing Q 3 and Q 4 to create reference signals, corresponding to the phase signals. In some aspects of the method, dividing the stream of data by two introduces a processing delay into the divided data. Then, the method further comprises: in response to the phase and reference signals, phase-locking a voltage controlled oscillator to generate the first and second clocks; delaying the received stream of binary data; and, using the first and second clocks to sample the delayed binary data.
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