发明名称 Stack semiconductor package ? manufacturing technique the same
摘要 PURPOSE: A stacked semiconductor package is provided to reduce warpage and minimize the possibility that a solder ball and a ball pad are separated by improving coherence by a reflow underfill adhesive including all solder balls. CONSTITUTION: A substrate(11,21) is prepared. A semiconductor chip(12,22) is located in the center of the substrate. The semiconductor chip is electrically connected to the substrate by a bonding wire(13,23). The semiconductor chip and the wire are molded and protected by an encapsulation material(14,24). The solder ball(15,25) is attached to a surface of the substrate to connect the electrical signal of the semiconductor chip to the outside. The first unit package includes the substrate, the semiconductor chip, the bonding wire, the encapsulation material and the solder ball. The second unit package has the same constitution as the first unit package. The second unit package is stacked on the first unit package wherein reflow underfill adhesive(3) is interposed between the first and second unit packages.
申请公布号 KR100617071(B1) 申请公布日期 2006.08.30
申请号 KR20020082565 申请日期 2002.12.23
申请人 发明人
分类号 H01L23/12 主分类号 H01L23/12
代理机构 代理人
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