发明名称 Method of predicting high-k semiconductor device lifetime
摘要 A preferred embodiment of the invention provides a method for testing a MISFET to determine the effect of hot carrier injection (HCI) on integrated circuit lifetime. The method comprises applying a positive stress voltage to a gate having a high-k dielectric, while simultaneously holding a drain voltage equal to the stress voltage. Using a stress voltage that is greater than a normal operating voltage accelerates the degradation and failure of the integrated circuit. Embodiments include monitoring electrical parameters such as threshold voltage, transconductance, linear drain current, or saturation drain current. A pre-selected shift in a monitored electrical parameter indicates device failure. Embodiments include analyzing the data by plotting the logarithm of an accelerated device lifetime versus the gate stress voltage. The device lifetime under operating conditions is predicted by extrapolating the plot for a given device operating voltage.
申请公布号 SG124324(A1) 申请公布日期 2006.08.30
申请号 SG20050001993 申请日期 2005.03.30
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. 发明人 TSAI CHING WEI;WANG JYH-HAUR;CHI MIN-HWA
分类号 主分类号
代理机构 代理人
主权项
地址