发明名称 |
Memory stack architecture for reduced TLB misses |
摘要 |
One embodiment disclosed relates to a computer system. The computer system includes a microprocessor, an operating system, and a memory system. The microprocessor includes a register stack and a register stack engine (RSE), and the operating system includes a kernel. The memory system is configured to have a single memory page that includes both a kernel stack and an RSE stack. The memory system may be further configured such that the kernel stack and the RSE stack grow in opposite directions and such that a uarea data structure is located between those two stacks.
|
申请公布号 |
US7100014(B2) |
申请公布日期 |
2006.08.29 |
申请号 |
US20030662734 |
申请日期 |
2003.09.15 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, LP. |
发明人 |
RUEMMLER CHRISTOPHER PHILIP;PAVLOVA FANI A. |
分类号 |
G06F12/00;G06F12/02;G06F12/10;G06F12/14 |
主分类号 |
G06F12/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|