| 摘要 |
A technique of minimizes circuit area on programmable logic with fracturable logic elements by using "balancing" in the technology mapping stage of the programmable logic computer-aided-design flow. A fracturable LE can be used for logic implementation in many ways, such as being used as one maximum-sized look-up table (LUT) or multiple smaller LUTs. One of more inputs of the multiple smaller LUTs may be shared. By balancing, this means mean that the technology mapping algorithm is tuned to use more small LUTs and fewer maximum-sized LUTs to implement the circuit. Although this is counterintuitive since the larger LUTs are more effective at absorbing gates, the technique achieves a smaller final circuit area by packing small LUTs into fracturable LEs.
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