| 摘要 |
By arranging floating spacer and gate non-volatile memory transistors in symmetric pairs, increased chip density may be attained. For each pair of such transistors, the floating gates are laterally aligned with floating spacers appearing on laterally outward edges of each floating gate. At laterally inward edges, the two transistors share a common source electrode. The transistors are independent of each other except for the shared source electrode. Tunnel oxide separated the floating spacer from the floating gate, but both the spacer and the gate are maintained at a common potential, thereby providing dual paths for charge exiting the tunnel oxide, as the charge is propelled by a programming voltage. The pairs of transistors can be aligned in columns with the direction of the columns orthogonal to the direction of the pairs, thereby forming a memory array.
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