| 摘要 |
<p>An adding circuit (42) which receives addend data and augend data, each of which consists of a plurality of bits, and sums the addend and augend data, comprises: a plurality of addition blocks (421 to 424), each of which is used to add a predetermined number of bits of the addend data (e.g. A0 to A3) to a like number of bits of the augend data (e.g. B0 to B3), and for outputting both the result (e.g. S0 to S3) obtained by adding the predetermined number of bits and a carry-out signal (C01), wherein, when a carry-out occurs for one of the addition blocks, in accordance with a carry-out signal from a lower rank and a set comprising the addend data and the augend data, the pertinent addition block responds to the pertinent carry-out, and wherein, when a carry-out does not occur for the addition block in accordance with the set comprising the addend data and the augend data, the pertinent addition block responds to the carry-out and generates a block addition end signal which indicates that the addition performed by the addition block has been completed. <IMAGE></p> |
