发明名称 Delayed locked loop (DLL) circuit providing adjustable delay of periodic input signal, with controllable, series connected delay elements, as delay chain
摘要 <p>Controllable delay elements (6) in series form delay chain (2) and phase detector (3) generates control signal, dependent on periodic input signal, and periodic signal delayed by delay chain.Circuit contains selection unit (7), coupled to each delay element to apply output signal of element to output of DLL circuit. Compensation circuit (9-11) modifies selection signal (AS) so that additional delay between periodic input and output signal of DLL circuit is compensated.</p>
申请公布号 DE102005008151(A1) 申请公布日期 2006.08.24
申请号 DE20051008151 申请日期 2005.02.23
申请人 INFINEON TECHNOLOGIES AG 发明人 JAKOBS, ANDREAS;HINZ, TORSTEN;ZARYOUH, BENAISSA
分类号 H03L7/081 主分类号 H03L7/081
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