| 摘要 |
Logic cell layout architecture having a shared boundary between at least two cells each forming logic functions, and a method ( 200 ) for designing a logic cell library having a shared boundary between at least two cells ( 12,32 ) is disclosed for increasing packing density and limiting the occurrence of stress between active areas and shallow trench isolation (STI) regions of logic cells within a standard cell library for semiconductor integrated circuits (IC).
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