| 摘要 |
A method ( 300 ) for optimising transistor performance in semiconductor integrated circuits built from standard cells ( 12 ), or custom transistor level layout, is disclosed. An active area of NMOS diffusion is extended with a joining area ( 102 ) between two adjacent cells ( 112 ) having the same net on diffusion at the adjacent edges of each cell. The diffusion area is extended to limit the occurrence of active and nonactive interface to minimise lattice strain effects and improve transistor performance.
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