发明名称 |
Multiple match detection circuit and method |
摘要 |
A multiple matchline sense circuit for detecting a single, more than one, or no match conditions during a search-and-compare operation of a content addressable memory is disclosed. The circuit compares the rising voltage rate of a multiple matchline to the rising voltage rate of a reference multiple matchline in order to generate a multibit result representing one of the three conditions. The circuit generates a self-timed control signal to end the search-and-compare operation, and to set the circuit to a precharge state. |
申请公布号 |
US7095640(B2) |
申请公布日期 |
2006.08.22 |
申请号 |
US20050285197 |
申请日期 |
2005.11.23 |
申请人 |
MOSAID TECHNOLOGIES INCORPORATED |
发明人 |
MA STANLEY JEH-CHUN;MA PETER P. |
分类号 |
G11C15/00;G01R25/00;G06F12/00;G11C7/00;G11C11/56;G11C15/04 |
主分类号 |
G11C15/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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