发明名称 Digital signal encoding device, digital signal decoding device, digital signal arithmetic encoding method and digital signal arithmetic decoding method
摘要 In a bit stream syntax containing compressed video slice data for compressed video data of a slice structure, a slice header for compressed video slice data has attached thereto a slice start code, a register reset flag indicating whether a register value, which designates a status of a codeword occurring in an arithmetic coding process, should be reset in the next transmission unit, an initial register value which indicates a register value to be used to start arithmetic coding/decoding to build/decompose the next transmission unit, only when the register reset flag indicates that the register should not be reset.
申请公布号 US7095344(B2) 申请公布日期 2006.08.22
申请号 US20030480046 申请日期 2003.12.09
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 SEKIGUCHI SHUNICHI;YAMADA YOSHIHISA;ASAI KOHTARO
分类号 H03M7/30;G06T9/00;H03M7/40;H04N7/12;H04N7/24;H04N7/26;H04N7/52 主分类号 H03M7/30
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