Circuit for optimizing the duty cycle of a received clock transmitted over a transmission line

摘要

Data signals are transmitted over transmission lines in groups to receivers in a receiving IC. Each group of data signals has a differential clock used in synchronizing and detecting the data signals. The data signal eye windows vary with timing jitter in the data signals relative to the clock edges and the asymmetry in a compensated clock signal detected from the differential clock using a duty cycle adjustment circuit. Error detection determines if the clock asymmetry is affecting the eye window of the data signals. Control signals selectively adjust the gain of differential stages generating the compensated clock to modify the duty cycle of the compensated clock. The eye window of the data signals are monitored and used as feedback to servo the control signals to optimize the duty cycle of the compensated clock signal for sampling the data signals.