| 摘要 |
PROBLEM TO BE SOLVED: To support a system design by integrally applying conditions from architecture design to logic synthesis. SOLUTION: A bus interface design support device 1 stores a complexity analysis library storing performance deterioration factors based on various complexities which are caused when an estimated bus interface is logically synthesized. In bus interface design, in addition to a condition to be logically satisfied as a bus protocol, influence of leak current which causes performance deterioration in mounting when the bus protocol is logically synthesized is reflected in reference to the complexity analysis library. According to this, a bus interface capable of realizing necessary performance from the viewpoint of the influence by leak current can be acquires as a layout on a chip. Therefore, conditions from bus architecture design to logic synthesis can be integrally applied to support the system design. COPYRIGHT: (C)2006,JPO&NCIPI
|
