发明名称 Broadcasting receiver
摘要 A PLL circuit compares a PCR with the output frequency of a voltage controlled oscillator (VCO), and returns a voltage value which is the result of the comparison to the VCO, so that a reference clock corresponding to the PCR is outputted from the VCO. A switch supplies a control voltage from the PLL circuit to the VCO when digital broadcasting is viewed, while feeding a fixed voltage from a fixed voltage power supply to the VCO when analog broadcasting is viewed, to stably output a clock having a frequency of 27 MHz irrespective of the change in the PCR.
申请公布号 US7092042(B2) 申请公布日期 2006.08.15
申请号 US20030443062 申请日期 2003.05.22
申请人 SANYO ELECTRIC CO., LTD. 发明人 IKEGUCHI YASUYUKI
分类号 H04N3/27;H03L7/06;H04N5/04;H04N5/12;H04N5/44;H04N5/445;H04N5/46;H04N9/00;H04N9/44 主分类号 H04N3/27
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