发明名称 Method for generating constrained component placement for integrated circuits and packages
摘要 A method for determining component placement in a circuit includes forming a tree structure that defines the placement of each of a plurality of components associated with the tree structure on a first side, a second side or on both sides of a symmetry line, with at least one component tagged for symmetric placement on both sides of a symmetry line; performing at least one search of the tree structure to determine an initial placement of a subset of the components; and performing another search of the tree structure to determine a final placement of the subset of components whereupon at least a part of each component tagged for symmetric placement is positioned on each side of the symmetry line. The method can be embodied as instructions stored on a computer readable medium which, when executed by a processor, cause the processor to implement the method.
申请公布号 US7093220(B2) 申请公布日期 2006.08.15
申请号 US20030674085 申请日期 2003.09.29
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 FALLON ELIAS;RUTENBAR ROB A.
分类号 G06F9/45;G06F17/50 主分类号 G06F9/45
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