发明名称 |
Delayed signal generation circuits and methods |
摘要 |
Circuitry for delaying a signal includes a phase-locked loop comprising one or more output nodes for outputting one or more output signals in response to a reference signal. A buffer is coupled to the output nodes of the phase-locked loop for receiving phase-locked loop output signals and outputs one or more buffered output signals. A multiplexing element receives the buffered output signals and a control signal and generates an operative buffered output signal in response to the control signal. A delay line receives a delay control input signal and the operative buffered output signal from the multiplexing element. The delay line outputs a delayed output signal in response to the delay control input signal.
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申请公布号 |
US2006176090(A1) |
申请公布日期 |
2006.08.10 |
申请号 |
US20050053695 |
申请日期 |
2005.02.08 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
GOWER KEVIN C.;SATHAYE SWATI |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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