发明名称 |
METHOD AND APPARATUS FOR MEMORY ACCESS SCHEDULING TO REDUCE MEMORY ACCESS LATENCY |
摘要 |
A device is presented including a memory controller. The memory controller is connected to a read request queue. A command queue is coupled to the memory controller. A memory page table is connected to the memory controller. The memory page table has many page table entries. A memory page history table is connected to the memory controller. The memory history table has many page history table entries. A pre-calculated lookup table is connected to the memory controller. The memory controller includes a memory scheduling process to reduce memory access latency. |
申请公布号 |
KR100610730(B1) |
申请公布日期 |
2006.08.09 |
申请号 |
KR20047004589 |
申请日期 |
2002.09.27 |
申请人 |
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发明人 |
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分类号 |
G06F13/00;G06F12/02;G06F13/16 |
主分类号 |
G06F13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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