发明名称 Ethernet switching architecture and dynamic memory allocation method for the same
摘要 This invention discloses a dynamic memory allocation method for an Ethernet switching architecture, which can resolve problems with the limitations of transmission bandwidths and transmission port counts in a conventional network packet switching. The method comprises steps of providing a plurality of input ports and output ports, providing a shared memory for storing packet segments of a plurality of packets, providing a first link RAM (Random Access Memory) for controlling a making and reading of a single linked list for the packet segments of each the plurality of packets, and providing a second link RAM serving as a FIFO (first in first out) device for co-managing an obtaining of the link address spaces at the corresponding input ports before the single linked list been made, and a releasing of the link address spaces at the corresponding output ports after the single linked list been read.
申请公布号 US7088730(B2) 申请公布日期 2006.08.08
申请号 US20020150252 申请日期 2002.05.15
申请人 ADMTEK INCORPORATED 发明人 HSU MENG-CHI;LO WEI-REN
分类号 H04L12/28;H04L12/56 主分类号 H04L12/28
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