发明名称 |
Chip scale package and method for manufacturing the same |
摘要 |
A chip scale package includes a patterned circuit layer attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive layer such that contact pads on a lower surface of the patterned circuit layer are electrically coupled to corresponding bonding pads on the semiconductor chip. The patterned circuit layer has a plurality of openings formed therein at locations corresponding to the contact pads such that each of the contact pads has a portion exposed from an upper surface of the patterned circuit layer through the corresponding opening. A plurality of metal bumps are respectively disposed in the openings and mounted to the exposed portions of the contact pads for making external electrical connection. The present invention further provides a method for manufacturing the chip scale package at the wafer-level.
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申请公布号 |
US2006170096(A1) |
申请公布日期 |
2006.08.03 |
申请号 |
US20050047617 |
申请日期 |
2005.02.02 |
申请人 |
YANG JUN Y;JOO YOU O;JUNG DONG P |
发明人 |
YANG JUN Y.;JOO YOU O.;JUNG DONG P. |
分类号 |
H01L23/34 |
主分类号 |
H01L23/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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