PROGRAM FREQUENCY DIVIDING TYPE FRACTIONAL PLL FREQUENCY SYNTHESIZER AND FREQUENCY DIVIDING SERIES COMPUTER THEREOF

摘要

PROBLEM TO BE SOLVED: To make phase noise of an output signal small in a fractional PLL frequency synthesizer.

SOLUTION: A series of integer dividing frequency of a frequency dividing circuit in a fractional PLL is stored in a memory device beforehand, is read out serially, and established. A nearer one of the most optimum in a series of integer dividing frequency is calculated using a heredity algorithm beforehand. A change of a generation can be performed by fulfilling a restricting condition for a series of integer dividing frequency, and optimality calculation can be efficiently performed by making each value of a series of integer dividing frequency as a gene in the heredity algorithm.

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