| 摘要 |
The SRAM cell 1 includes inverters 10, 20 , N-type FETs (Field Effect Transistors) 32, 34, 36, 38 , word lines 42, 44 , and bit lines 46, 48 . A gate width W 2 and gate length L 2 of the FETs 32, 34, 36, 38 are equal to a gate width W 3 and gate length L 3 of the FETs 12, 22 , respectively. In particular, in this embodiment, a gate width W 4 and gate length L 4 of the FETs 14, 24 are also equal to W 2 (=W 3 ) and L 2 (=L 3 ), respectively. Namely, the SRAM cell 1 is designed in such a manner that W 2 =W 3 =W 4 , and L 2 =L 3 =L 4.
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