Nonvolatile semiconductor storage device

摘要

The disclosed flash memory is provided with a majority logic circuit 3 and shift registers 6 ₁ to 6 ₃. Three out of the banks 2 a to 2 c of the memory respectively include management information areas KAs to store binary management information comprising power supply trimming data and bitline restoration data. During initialization of the flash memory, the majority logic circuit 3 performs error correction on management information bits retrieved from the management information areas KAs and outputs that information to a trimming/restoration data buffer 11 , thus providing highly reliable management information very quickly. The shift registers 6 ₁ to 6 ₃ delay a control signal that is output from a control circuit 12 by a certain period of time before outputting the control signal to sense amplifiers 4 ₂ to 4 ₄. This delay makes it possible to make the operating currents of the banks 2 a to 2 d start to flow at different times and to suppress a peak current flowing in the flash memory.