发明名称 |
Phase swallow device and signal generator using the same |
摘要 |
A signal generator for generating a clock with lower jitter. The signal generator includes a multi-phase clock generator for generating a plurality of multi-phase reference clocks with same frequency, a multiplexer for selecting one reference clock as an output clock according to a phase selecting signal, a phase-swallow control unit having a comparator for comparing a swallow value with a reference value out of order and outputting the comparing result as a swallow control signal, and a clock selector for receiving the swallow control signal and generating the phase selecting signal. Because the reference value is provided by a counter in bit-reversed, the swallow control signal is dispersed smoothly and the jitter of the output clock is reduced.
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申请公布号 |
US7084687(B2) |
申请公布日期 |
2006.08.01 |
申请号 |
US20040896118 |
申请日期 |
2004.07.22 |
申请人 |
REALTEK SEMICONDUCTOR CORP. |
发明人 |
WENG WEN-SHIUNG;CHANG MING-CHUN;KUAN CHI-KUNG;CHANG YI-SHU;TAI KUO-LIN |
分类号 |
G06F1/04;G06F1/10;H03L7/00 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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