发明名称 CIRCUIT OPERATION VERIFICATION METHOD, CIRCUIT OPERATION VERIFICATION DEVICE, AND COMPUTER PROGRAM
摘要 PROBLEM TO BE SOLVED: To provide a circuit operation verification method, a circuit operation verification device, and a computer program, capable of correctly and speedily verifying whether or not a circuit element built in a semiconductor integrated circuit malfunctions by considering each voltage drop of power supply wiring and grounding wiring. SOLUTION: Based on a function showing the relation between the total amount of voltage drops and the amount of a delay variation, the amount of an allowable power supply voltage dropΔV<SB>DDY</SB>and the amount of an allowable grounding voltage dropΔV<SB>SSY</SB>corresponding to the amount of the delay variation P<SB>Y</SB>which satisfies design constraints are determined, and when the amount of a power supply voltage dropΔV<SB>DDDC</SB>of the circuit element determined based on mask layout data is smaller thanΔV<SB>DDY</SB>, or the amount of a grounding voltage dropΔV<SB>SSDC</SB>is smaller thanΔV<SB>SSY</SB>, the circuit element is determined to malfunction. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006195754(A) 申请公布日期 2006.07.27
申请号 JP20050006895 申请日期 2005.01.13
申请人 SHARP CORP 发明人 NAKABAYASHI TAMIYO
分类号 G06F17/50;G01R31/28;H01L21/82;H01L21/822;H01L27/04 主分类号 G06F17/50
代理机构 代理人
主权项
地址