Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC)

摘要

An apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) comprises operating a clock associated with the IC at a frequency (f_TARGET) at which IC operation is sought to be determined, measuring the actual clock period (T_CLOCK-OUT) at a clock output, scan testing the IC, measuring the actual clock period (T_{SCAN-CLOCK-OUT}) at the clock output, determining a delay by calculating the difference between T_{SCAN-CLOCK-OUT} and T_CLOCK-OUT, and compensating for the delay by increasing the clock frequency during scan test.