DUAL LOOP PLL AND MULTIPLICATION CLOCK GENERATION APPARATUS

摘要

PROBLEM TO BE SOLVED: To provide a dual loop PLL (phase locked loop) capable of shortening lock-up time at initial start and to provide a multiplication clock generation apparatus capable of contributing reduction in power consumption.

SOLUTION: The dual loop PLL comprises a phase comparing loop having a phase comparator 1 for comparing phases with each other and a frequency comparing loop having a frequency comparator 7 for comparing frequencies with each other. The frequency comparator 7 performs frequency comparison by an input signal entered from a calibration clock line CLcal 18, which is different from a reference clock signal entered from an external reference clock line CLex 11 to be used for the phase comparator 1. The multiplication clock generation apparatus is constituted by using the dual loop PLL.

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