发明名称 METHOD FOR CONTROLLING POWER OF ADDRESS CONVERSION BUFFER AND DEVICE THEREOF
摘要 <p><P>PROBLEM TO BE SOLVED: To reduce wasteful power consumption by performing cutoff control of an entry which is not used for a long time in a TLB. <P>SOLUTION: In a power controller of an address conversion buffer of a central processor having a plurality of entries which convert a logical address into a physical address and an entry replacement mechanism for replacing the entries, it has an entry selection part 502 which selects an entry according to judgment criteria by which judgment is performed based on information to be reference for selecting the entry and weighting operation of each piece of information among the plurality of entries which the address conversion buffer has and a power control part 503 which controls power of the selected entry. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p>
申请公布号 JP2006190341(A) 申请公布日期 2006.07.20
申请号 JP20060101850 申请日期 2006.04.03
申请人 FUJITSU LTD 发明人 YOSHIMI KOICHI
分类号 G06F12/08;G06F12/10;G06F12/12 主分类号 G06F12/08
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