发明名称 System clock distributing apparatus and system clock distributing method
摘要 In providing a system clock distributing apparatus and a system clock distributing method for reducing a skew of a system clock and a synchronizing signal at low cost, a system clock distributing apparatus for matching the timing of data by using the synchronizing signal includes an oscillator 1 that generates a periodical synchronizing signal and a PLL 2, a memory that stores the data, at least one CPU 13 that conducts a computing process using the data stored in the memory, at least one MAC 14 that controls an access from the CPU 13 to the memory, and at least one NB 12 that generates the system clock having a frequency that is an integral multiple of the synchronizing signal, and controls the CPU 13 and the MAC 14 based on the operation by the system clock.
申请公布号 EP1681610(A2) 申请公布日期 2006.07.19
申请号 EP20050252671 申请日期 2005.04.28
申请人 FUJITSU LIMITED 发明人 UCHIDA, NOBUO
分类号 G06F1/10;G06F1/04 主分类号 G06F1/10
代理机构 代理人
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