| 摘要 |
A microprocessor apparatus for exclusive prefetch and initialization of a cache line from memory, including translation logic and execution logic. The translation logic translates an allocate and initialize instruction into a micro instruction sequence that directs a microprocessor to prefetch a cache line in an exclusive state and to initialize the cache line to a specified value, where the allocate and initialize instruction is encoded to direct the microprocessor to prefetch the cache line in the exclusive state and to initialize the cache line to the specified value. The execution logic receives the micro instruction sequence, and issues a transaction over a memory bus that requests the cache line in the exclusive state. Upon receipt, the execution logic initializes the cache line to the specified value. The allocation and initialization of the cache line occurs in parallel with execution of other instructions in a program flow of an application program.
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