发明名称 |
Method and BIST architecture for fast memory testing in platform-based integrated circuit |
摘要 |
The present invention provides a method and BIST architecture for fast memory testing in a platform-based integrated circuit. The method may include steps as follows. An Mem-BIST controller transmitter is started to generate input signals for a memory in a platform using a deterministic and unconditional test algorithm. The input signals are delayed by a first group of pipelines by n clock cycles. The delayed input signals are received by the memory and an output signal is generated by the memory. The output signal is delayed by a second pipeline by m clock cycles. An Mem-BIST controller receiver is started to receive the delayed output signal for comparison.
|
申请公布号 |
US2006156088(A1) |
申请公布日期 |
2006.07.13 |
申请号 |
US20040999493 |
申请日期 |
2004.11.30 |
申请人 |
ANDREEV ALEXANDER E;BOLOTOV ANATOLI A;SCEPANOVIC RAOKO |
发明人 |
ANDREEV ALEXANDER E.;BOLOTOV ANATOLI A.;SCEPANOVIC RAOKO |
分类号 |
G11C29/00 |
主分类号 |
G11C29/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|