发明名称 TRACK BUFFER IN A PARALLEL DECODER
摘要 <p>A method (700) and apparatus (600) are described for performing 2&lt;SUP&gt;M-1 &lt;/SUP&gt;parallel ACS operations to generate 2&lt;SUP&gt;M&lt;/SUP&gt; path metric outputs and buffering the 2&lt;SUP&gt;M&lt;/SUP&gt; path metric outputs in connection with a track buffer (112) in an Ultrawide Bandwidth (UWB) receiver for decoding a message sequence encoded according to a convolutional code. Contents of the track buffer are updated in accordance with Register Exchange and outputs from the track buffer can further be input to a voting unit (114) where a voting scheme can be applied and a decision rendered as to the originally transmitted message sequence.</p>
申请公布号 WO2006073732(A2) 申请公布日期 2006.07.13
申请号 WO2005US45544 申请日期 2005.12.15
申请人 FREESCALE SEMICONDUCTOR, INC.;WANG, BO;MACIAS, ADRIAN R. 发明人 WANG, BO;MACIAS, ADRIAN R.
分类号 H03M13/00 主分类号 H03M13/00
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