| 摘要 |
A systolic squarer comprises a systolic array classified into five cell modules by pipeline and regulation according to each operational circuit. According to fundamental structures, the five cell modules constitute the systolic squarer. Each of the cell modules is selected from a group consisting of plural full adders, plural half adders and plural AND gates. Thereby, the five cell modules are suitable for applying to process a great number of digital signals of data, speeding up processing time, and reducing hardware cost and power consumption.
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