| 摘要 |
The semiconductor device comprises a first conductive pattern 42 , a second conductive pattern 42 formed adjacent to the first conductive pattern 42 , a first conductor plug 28 formed below a prescribed region of the first conductive pattern 42 , a second conductor plug 62 <SUB>n </SUB>formed over a prescribed region of the first conductive pattern 42 , a third conductor plug 28 formed below a prescribed region of the second conductive pattern 42 , which is adjacent to a prescribed region of the first conductive pattern 42 , a fourth conductor plug 62 <SUB>n+1 </SUB>formed over a prescribed region of the second conductive pattern 42 , a third conductive pattern 64 formed above the first conductive pattern 42 and connected to the second conductor plug 62 a, and a fourth conductive pattern 64 formed above the second conductive pattern 42 and connected to the fourth conductor plug 62 . The fourth conductor plug 62 <SUB>n+1 </SUB>is arranged a position which is offset from the second conductor plug 62 <SUB>n</SUB>. The conductor plugs 62 <SUB>n</SUB> , 62 <SUB>n+1 </SUB>are offset each other in the longitudinal direction of the interconnections, whereby the parts of the interconnections having an increased width can be distanced from each other. Thus, the interconnections can be arranged at a small pitch without using an ArF exposure system and a half tone phase shift mask, which are expensive. Accordingly, the semiconductor device of high integration is provided at low costs while ensuring high fabrication yields.
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