发明名称 Image processing module with less line buffers
摘要 An image processing module with less line buffers is provided. The image processing module receives an original image signal to drive a display panel. The image processing module includes a timing controller and a scaler. The timing controller includes a line buffer and a control unit. The line buffer registers the original image signal and outputs a storage image signal. The scaler receives the storage image signal, adjusts the resolution of the storage image signal, and outputs a scaled image signal to the control unit according to the resolution of the storage image signal. The control unit receives the scaled image signal and outputs a display signal to drive the display panel according to the scaled image signal.
申请公布号 US2006146076(A1) 申请公布日期 2006.07.06
申请号 US20050296690 申请日期 2005.12.08
申请人 HUANG CHUNG-HSUN;CHEN KUEI-HSIANG 发明人 HUANG CHUNG-HSUN;CHEN KUEI-HSIANG
分类号 G09G5/02 主分类号 G09G5/02
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