| 摘要 |
PROBLEM TO BE SOLVED: To provide a logic synthesizer capable of preventing unnecessary load distribution and performing load distribution in consideration of the optimal cell arrangement and a wiring area at the time of layout in logic synthesis of LSI design. SOLUTION: A room for improvement in layout remains at the time of logic synthesis by analyzing an RTL (s2), extracting a high fan-out network (s3) and inserting a buffer for a clock tree to be performed at the time of layout into the RTL to the network (s4) and the optimal layout in consideration of the cell arrangement, the wiring area is performed by a layout tool. In addition, since the library is analyzed (s6) and a cell with large drive capacity is not used at the time of logic synthesis (s7), the optimal layout by converging timing is performed by re-mapping a high drive cell to a place where timing is severe at the time of layout. COPYRIGHT: (C)2006,JPO&NCIPI
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