| 摘要 |
A method and a system for the detection and correction of errors in memory systems is disclosed. In one embodiment, a method of error detection in a memory system having a plurality (m>1) of memory devices includes generating check bits for each of a plurality of data sets, dividing each memory device into a plurality (n>1) of segments. The plurality of data sets are interleaved to form a plurality (p>1) of words. Each word includes at least one segment from two or more of the memory devices. Detection and correction may utilize one or more parallel Reed-Solomon decoder and encoder. The system and method allow for the efficient detection and/or correction of memory device errors and bit errors in one or more memory devices.
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