Clock synchronization circuit

摘要

A clock synchronization circuit for synchronizing a first clock signal (Phi₁) and a second clock signal (Phi₂) for data transfer from a first function block ( 2 ), which is clocked by the first clock signal (Phi_D) at a relatively high clock frequency (f_Phi1), to a second function block ( 3 ), which is clocked by the second clock signal (Phi₂) at a relatively low clock frequency (f_Phi2), where the clock synchronization circuit ( 24 ) has a sampling unit ( 30 ) for sampling the second clock signal (Phi₂) using the first clock signal (Phi₁) in order to generate samples (S) and edge detection values (E) of the sampled second clock signal (Phi₂), a logic circuit ( 38 ), clocked using the first clock signal (Phi₁), for outputting the generated samples (S) or the generated edge detection values (E) as a reconstructed second clock signal (Phi₂') in the time frame of the first clock signal (Phi₁) at an output of the logic circuit ( 38 ), where the output ( 42 ) of the logic circuit is reset after outputting a value (S, E) until the logic circuit ( 38 ) receives an Enable signal, where the logic circuit ( 38 ) generates an Edge-Too-Early signal (ETE) if the generated edge detection value (E) is at logic high before the Enable signal is received, and generates an Edge-Too-Late signal (ETL) if the Enable signal is received before the generated edge detection value (E) is at logic high, and a signal delay circuit, clocked using the first clock signal (Phi₁), which delays the reconstructed second clock signal (Phi₂') with a variable time delay (tau) on the basis of the Edge-Too-Early signal (ETE) and the Edge-Too-Late signal (ETL).