发明名称 METHOD FOR FORMING SCAN CHAIN AND METHOD FOR TESTING INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To obtain a scan chain forming method for shortening the length of scan chains and making the length of divided scan chains substantially equal at the same time because a method is effective which divides a scan chain into a plurality of scan chains and simultaneously performs a test in parallel in order to shorten a time required for a scan test. SOLUTION: First, a test synthetic tool is used to form one scan chain, and next, an arrangement tool is used to rearrange a flip-flop circuit constituting the scan chain to form a line file of shortened flip-flop chains. In the line file, divided line files are created so as to make the number of flip-flops substantially equal. The line files are used to form a plurality of divided scan chains. An input/output terminal of each scan chain is connected to a scan control circuit, and when an integrated circuit is tested, input/output terminals of a plurality of grouped scan chains are connected to a prescribed pad and a scan test is performed in parallel. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006163688(A) 申请公布日期 2006.06.22
申请号 JP20040352603 申请日期 2004.12.06
申请人 FUJITSU LTD 发明人 HASHIMOTO YOSHIJI;YAMADA MAKOTO;IDA TAKAHIRO;OHASHI KATSUHITO
分类号 G06F17/50;G01R31/28;H01L21/822;H01L27/04 主分类号 G06F17/50
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