| 摘要 |
An n-stage charge pump contains n primary capacitive elements (C<SUB>C1</SUB>-C<SUB>Cn </SUB>or C<SUB>D1</SUB>-C<SUB>Dn</SUB>), n+1 charge-transfer cells ( 60 <SUB>1</SUB>- 60 <SUB>n+1</SUB> , 110 <SUB>1</SUB>- 110 <SUB>n+1</SUB> , 120 <SUB>1</SUB>- 120 <SUB>n+1</SUB>, or 130 <SUB>1</SUB>- 130 <SUB>n+1</SUB>) respectively sequentially designated as the first through (n+1)th cells, and sources of first and second clock signals (V<SUB>CKP </SUB>and {overscore (V<SUB>CK P </SUB>or V<SUB>CKP1 </SUB>and V<SUB>CKP2</SUB>) approximately inverse to each other. Each pump stage ( 62 <SUB>i</SUB> , 112 <SUB>i</SUB> , 122 <SUB>i</SUB>, or 132 <SUB>i</SUB>) includes one (C<SUB>Ci </SUB>or C<SUB>Di</SUB>) of the capacitive elements and a corresponding one ( 60 <SUB>i</SUB> , 110 <SUB>i</SUB> , 120 <SUB>i</SUB>, or 130 <SUB>i</SUB>) of the first through nth charge-transfer cells. Each cell contains a charge-transfer FET (P<SUB>Ti </SUB>or N<SUB>Ti</SUB>). A pair of side FETs (P<SUB>Si </SUB>and P<SUB>Di </SUB>or N<SUB>Si </SUB>and N<SUB>Di</SUB>) are provided in the first cell, in the (n+1)th cell, and normally in each remaining cell. The side FETs in the first cell or/and the (n+1) cell are connected in such a manner as to avoid undesired bipolar action that could cause degradation in the pump's voltage gain.
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