| 摘要 |
A method, test mode circuit and system for a combined write window and retention test for a memory device that is faster than techniques heretofore known. The combined write window and retention test procedure involves controlling time intervals during which wordlines are activated and deactivated and bitlines are grounded or connected to a bitline high voltage such that the wordlines are activated while bitlines are either grounded or at the bitline high voltage. During a first time interval after the wordlines are activated a first value (e.g., 0 V) is written to storage cells associated with the activated wordlines. During a second time interval after a second activation of the wordlines, a second value (a non-zero logic "1" V) is written to storage cells associated with activated wordlines. The second time interval has a duration that establishes write window test conditions. After expiration of a third time interval corresponding to a retention time interval, the storage cells are read and a determination is made whether a storage cell has passed or failed a combined write window and retention test based on a value read from the storage cell. |
