| 摘要 |
PROBLEM TO BE SOLVED: To provide a logic synthesis system capable of implementing a fast logic synthesis process while avoiding wasting time during logic synthesis. SOLUTION: A first logic synthesis part 1 performs logic synthesis on the basis of an RTL 101. A logic resynthesis path extracting part 2 extracts paths that do not meet a desired operating speed from the results of logic synthesis coming from the first logic synthesis part 1. A second logic synthesis part 3 performs logic synthesis only on the paths extracted by the logic resynthesis path extracting part 2. COPYRIGHT: (C)2006,JPO&NCIPI
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