| 摘要 |
PURPOSE:To speed up the whole instruction cycle by dividing a branch instruction into two-step instructions and executing an instruction cycle for forming a selecting signal of the next address precedently. CONSTITUTION:When a branch instruction is to be stored in an ROM1, the branch instruction is divided into a selecting signal forming instruction for designating the formation of a selecting signal and a next address selecting instruction for designating the selection of the next address. When the branch instruction is outputted, a selecting signal formation instruction 2-1 is outputted and then a next address selecting instruction 2-2 is outputted. Consequently, a condition selector 8 and a selecting signal generator 9 are controlled by the instruction 2-1 and a branched address selecting signal, i.e. a selecting signal (a 4-bit signal in this case) for selecting any one of addresses specified by a program counter 4, a stack 5, an interrupted address generator 6, and the next address selecting instruction 2-2 is formed and latched in a register 10.
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