发明名称 |
DELAYED LOCKED LOOP PHASE BLENDER CIRCUIT |
摘要 |
Techniques and circuit configurations for fine phase adjustments, for example, in a delay-locked loop (DLL) circuit are provided. Multiple phase signals may be generated from a single current source by selectively coupling one or more delay elements to an output node of the current source. The delay elements may vary the timing of a signal generated by switching the current source. |
申请公布号 |
KR20060067976(A) |
申请公布日期 |
2006.06.20 |
申请号 |
KR20067008287 |
申请日期 |
2006.04.28 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
HAN, JONG HEE;KIM, JUNG PILL |
分类号 |
H03L7/06;H03K5/00;H03K5/13;H03L7/08;H03L7/081 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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